Design of Modified Canny Edge Detector Based on FPGA for Portable Device

Authors

  • Pallavi Ramgundewar Electronics and Telecommunication Engineering GHRIETW, RTMN University Nagpur, India
  • S. P. Hingway Electronics and Communication Engineering GHRIETW, RTMN University Nagpur, India
  • K. Mankar Electronics and Communication Engineering GHRIETW, RTMN University Nagpur, India

DOI:

https://doi.org/10.53555/nneee.v2i7.184

Keywords:

Distributed Processing, Canny Edge Detector, High Throughput,, Parallel Processing, FPGA

Abstract

Edge detection is one of the key stages in image processing and object reorganization. The Canny Edge Detector is one of the most widely used edge detection algorithm due to its superior performance. In this paper, we propose a mechanism to implement the Canny algorithm at the block level without any loss in edge detection performance compared with the original frame-based Canny algorithm. Directly applying the original Canny Edge detection algorithm at the blocklevel leads to excessive edges in smooth regions and to loss of significant edges in high-detailed regions since the original Canny computes the high and low thresholds based on the frame-level statistics. To solve this problem, we present a modified Canny edge detection algorithm that adaptively computes the edge detection thresholds based on the block type and the local distribution of the gradients in the image block. Here we propose the design of modified Canny Edge detection algorithm that results in significantly reduced memory requirement, decrease in latency, increase throughput, with no loss in edge detection performance as compare to original Canny Detector Algorithm. Here we are using matlab to convert image into text/pixel value.

References

Paulo Ricardo Possa, Sidi Ahmed Mahmoudi, Naim Harb, Carlos Valderrama and Pierre Manneback, “A MultiResolution FPGA-Based Architecture for Real-Time Edge and Corner Detection”, IEEE TRANSACTIONS ON COMPUTERS, VOL. XX, NO. XX, JANUARY 2013.

K. Park, N. Singhal, M. H. Lee, S. Cho, and C. W. Kim, “Design and performance evaluation of image processing algorithms on GPUs,” IEEE Trans. Parallel Distrib. Syst., vol. 22, no. 1, pp. 91–104, Jan. 2011.

N. D. Narvekar and L. J. Karam, “A no-reference image blur metric based on the cumulative probability of blur detection (CPBD),” IEEE Trans. Image Process., vol. 20, no. 9, pp. 2678–2683, Sep. 2011.

Gentsos, C. Sotiropoulou, S. Nikolaidis, and N. Vassiliadis, “Real-time canny edge detection parallel implementation for FPGAs,” in Proc. IEEE ICECS, Dec. 2010, pp. 499–502.

W. He and K. Yuan, “An improved canny edge detector and its realization on FPGA,” in Proc. IEEE 7th WCICA, Jun. 2008, pp. 6561–6564.

V. Rao and M. Venkatesan, “An efficient reconfigurable architecture and implementation of edge detection algorithm using handle-C,” in Proc. IEEE Conf. ITCC, vol. 2. Apr. 2004, pp. 843–847.

S. Varadarajan, C. Chakrabarti, L. J. Karam, and J. M. Bauza,“A distributed psycho-visually motivated Canny edge detector,” IEEE ICASSP, pp. 822 –825, Mar. 2010.

Q. Xu, C. Chakrabarti, and L. J. Karam, “A distributed Canny edge detector and its implementation on FPGA,” in Proc. DSP/SPE),Jan. 2011, pp. 500–505.

Mat lab website, http:// www.mathworks.com

Published

2015-07-31

How to Cite

Ramgundewar, P., Hingway, S. P. ., & Mankar, K. (2015). Design of Modified Canny Edge Detector Based on FPGA for Portable Device. Journal of Advance Research in Electrical & Electronics Engineering (ISSN 2208-2395), 2(7), 05-11. https://doi.org/10.53555/nneee.v2i7.184