Design of Asynchronous Viterbi Decoder using Dual-Rail Protocol for Low Power Consumption

Authors

  • Sonali V. Mothe Student, M.Tech, (Communication Engineering) Electronics and Telecommunication Engineering G. H. Raisoni College of Engineering, Nagpur, India
  • Surekha Tadse Kalam Research Scholar, Electronics and Telecommunication Engineering G. H. Raisoni College of Engineering Nagpur, India

DOI:

https://doi.org/10.53555/nnmce.v2i3.352

Keywords:

Viterbi Algorithm, Synchronous, Asynchronous, Handshake Protocol (Dual Rail Protocol).

Abstract

Paper shows the review of asynchronous Viterbi decoder using hand shake protocol as Dual – Rail protocol. Viterbi decoders are used for decoding convolution forward error correction codes in a large proportion of digital transmission systems including mobile phones and digital television. For portable applications, the battery size and lifetime is of commercial importance as is the size of the electronics. The approach adopted in the Viterbi design is to use a self-timed (or asynchronous) timing strategy. This saves power through not having to generate or distribute a global clock. Instead, timing between blocks is performed by local handshake signals. This enables an asynchronous system to only consume power when doing useful work and to have an idle power of near zero. Furthermore, there is an inherent advantage to asynchronous systems in that a system can switch almost instantaneously between the idle state and maximum activity; this is much more difficult to organize in a clocking system.

References

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Published

2015-03-31

How to Cite

Mothe, S. V., & Kalam, S. T. (2015). Design of Asynchronous Viterbi Decoder using Dual-Rail Protocol for Low Power Consumption. Journal of Advance Research in Mechanical and Civil Engineering (ISSN: 2208-2379), 2(3), 46-49. https://doi.org/10.53555/nnmce.v2i3.352